XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
This addresses the problem of enabling efficient CNN deployment in low-power embedded systems, representing a domain-specific incremental improvement.
The paper tackles the high power and memory demands of deploying CNNs in low-power embedded systems by introducing XNORBIN, a hardware accelerator for binary CNNs that achieves an energy efficiency of 95 TOp/s/W and an area efficiency of 2.0 TOp/s/MGE.
Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows CNNs sustain extreme quantization, binarizing their weights and intermediate feature maps, thereby saving 8-32\x memory and collapsing energy-intensive sum-of-products into XNOR-and-popcount operations. We present XNORBIN, an accelerator for binary CNNs with computation tightly coupled to memory for aggressive data reuse. Implemented in UMC 65nm technology XNORBIN achieves an energy efficiency of 95 TOp/s/W and an area efficiency of 2.0 TOp/s/MGE at 0.8 V.