Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
It provides a comparative analysis for researchers and engineers working on FPGA-based CNN acceleration, identifying gaps and future directions, but is incremental as a survey.
This paper surveys existing toolflows for mapping Convolutional Neural Networks (CNNs) onto FPGAs, comparing their characteristics and proposing a uniform evaluation methodology to address challenges from recent CNN trends.
In the past decade, Convolutional Neural Networks (CNNs) have demonstrated state-of-the-art performance in various Artificial Intelligence tasks. To accelerate the experimentation and development of CNNs, several software frameworks have been released, primarily targeting power-hungry CPUs and GPUs. In this context, reconfigurable hardware in the form of FPGAs constitutes a potential alternative platform that can be integrated in the existing deep learning ecosystem to provide a tunable balance between performance, power consumption and programmability. In this paper, a survey of the existing CNN-to-FPGA toolflows is presented, comprising a comparative study of their key characteristics which include the supported applications, architectural choices, design space exploration methods and achieved performance. Moreover, major challenges and objectives introduced by the latest trends in CNN algorithmic research are identified and presented. Finally, a uniform evaluation methodology is proposed, aiming at the comprehensive, complete and in-depth evaluation of CNN-to-FPGA toolflows.