LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection
This addresses hardware security for FPGA and ASIC designers by providing incremental improvements in obfuscation resilience against SAT attacks.
The authors tackled the problem of protecting intellectual property in FPGA bitstreams and ASIC netlists by proposing LUT-Lock, a novel LUT-based obfuscation algorithm that forces a near exponential increase in SAT attack execution time with respect to the number of obfuscated gates, making attacks unreasonably long.
In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist obfuscation algorithm, for protecting the intellectual property that is mapped to an FPGA bitstream or an ASIC netlist. We, first, illustrate the effectiveness of several key features that make the LUT-based obfuscation more resilient against SAT attacks and then we embed the proposed key features into our proposed LUT-Lock algorithm. We illustrates that LUT-Lock maximizes the resiliency of the LUT-based obfuscation against SAT attacks by forcing a near exponential increase in the execution time of a SAT solver with respect to the number of obfuscated gates. Hence, by adopting LUT-Lock algorithm, SAT attack execution time could be made unreasonably long by increasing the number of utilized LUTs.