Efficient Design of Hardware-Enabled Reservoir Computing in FPGAs
This work addresses the need for reduced expert knowledge and optimization effort in designing hardware-enabled reservoir computing, particularly for ultrahigh-speed implementations, though it appears incremental as it combines existing techniques.
The paper tackled the problem of efficiently optimizing and implementing reservoir computing hardware by adapting the input mask to data structure using linear autoencoders and employing genetic algorithms for optimization, resulting in dramatically reduced evaluation numbers and establishing a strategy for self-adaptive machine learning hardware, with validation on FPGA-based hardware.
In this work, we propose a new approach towards the efficient optimization and implementation of reservoir computing hardware reducing the required domain expert knowledge and optimization effort. First, we adapt the reservoir input mask to the structure of the data via linear autoencoders. We therefore incorporate the advantages of dimensionality reduction and dimensionality expansion achieved by conventional algorithmically efficient linear algebra procedures of principal component analysis. Second, we employ evolutionary-inspired genetic algorithm techniques resulting in a highly efficient optimization of reservoir dynamics with dramatically reduced number of evaluations comparing to exhaustive search. We illustrate the method on the so-called single-node reservoir computing architecture, especially suitable for implementation in ultrahigh-speed hardware. The combination of both methods and the resulting reduction of time required for performance optimization of a hardware system establish a strategy towards machine learning hardware capable of self-adaption to optimally solve specific problems. We confirm the validity of those principles building reservoir computing hardware based on a field-programmable gate array.