f-CNN$^{\text{x}}$: A Toolflow for Mapping Multi-CNN Applications on FPGAs
This work addresses the problem of optimizing multi-CNN systems on FPGAs for developers in fields like autonomous vehicles, offering incremental improvements in toolflow automation and scheduling.
The paper tackles the challenge of efficiently mapping multiple CNNs onto a single FPGA for latency-sensitive applications by proposing f-CNN^x, an automated toolflow that optimizes resource allocation and memory bandwidth scheduling. The result shows designs outperforming contention-unaware FPGA mappings by up to 50% and achieving up to 6.8x higher performance-per-Watt compared to optimized GPU designs.
The predictive power of Convolutional Neural Networks (CNNs) has been an integral factor for emerging latency-sensitive applications, such as autonomous drones and vehicles. Such systems employ multiple CNNs, each one trained for a particular task. The efficient mapping of multiple CNNs on a single FPGA device is a challenging task as the allocation of compute resources and external memory bandwidth needs to be optimised at design time. This paper proposes f-CNN$^{\text{x}}$, an automated toolflow for the optimised mapping of multiple CNNs on FPGAs, comprising a novel multi-CNN hardware architecture together with an automated design space exploration method that considers the user-specified performance requirements for each model to allocate compute resources and generate a synthesisable accelerator. Moreover, f-CNN$^{\text{x}}$ employs a novel scheduling algorithm that alleviates the limitations of the memory bandwidth contention between CNNs and sustains the high utilisation of the architecture. Experimental evaluation shows that f-CNN$^{\text{x}}$'s designs outperform contention-unaware FPGA mappings by up to 50% and deliver up to 6.8x higher performance-per-Watt over highly optimised GPU designs for multi-CNN systems.