Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
This addresses the gap between architectural and physical designs in VLSI for adder optimization, but it is incremental as it builds on existing synthesis algorithms.
The paper tackles the problem of sub-optimal adder designs after physical implementation by enhancing a prefix adder synthesis algorithm to explore a wider architectural solution space and using machine learning with active learning to predict the Pareto frontier in the physical domain, achieving high-quality results over a wide design space.
In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is utilized to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs.