Memristor-based Synaptic Sampling Machines
This work addresses the need for efficient hardware in IoT edge devices, but it is incremental as it focuses on implementing an existing algorithm in hardware.
The authors tackled the problem of hardware acceleration for neural networks in edge computing by proposing a memristor-based circuit design for Synaptic Sampling Machines, achieving a hardware implementation that enables real-time processing.
Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampling algorithm that demonstrated promising results on software for hardware implementation.