Sparse Winograd Convolutional neural networks on small-scale systolic arrays
This work addresses energy efficiency and speed challenges for FPGA accelerators in deep learning, though it is incremental as it builds on existing sparse and Winograd methods.
The paper tackles the imbalance between computation throughput and memory support in FPGA-based deep learning accelerators by implementing a design combining sparse Winograd convolution, small-scale systolic arrays, and tailored memory layout, achieving 20x-30x energy efficiency and over 5x speedup on VGG16 compared to dense implementations.
The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement an accelerator on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on VGG16 show that it achieves very high computational resource utilization, 20x ~ 30x energy efficiency, and more than 5x speedup compared with the dense implementation.