Memristor-based Deep Convolution Neural Network: A Case Study
This work addresses hardware acceleration for deep learning, specifically for CNNs, but is incremental as it focuses on optimizing existing memristor-based methods for a specific case study.
The paper tackled the efficient implementation of large-scale high-dimensional convolution using realistic memristor-based circuits, developing an improved conversion algorithm to minimize error and finding that 8-bit ADC/DAC is necessary to preserve software-level classification accuracy in ResNet-20 simulations.
In this paper, we firstly introduce a method to efficiently implement large-scale high-dimensional convolution with realistic memristor-based circuit components. An experiment verified simulator is adapted for accurate prediction of analog crossbar behavior. An improved conversion algorithm is developed to convert convolution kernels to memristor-based circuits, which minimizes the error with consideration of the data and kernel patterns in CNNs. With circuit simulation for all convolution layers in ResNet-20, we found that 8-bit ADC/DAC is necessary to preserve software level classification accuracy.