FPGA-based Acceleration System for Visual Tracking
This work addresses the need for faster and more power-efficient visual tracking systems for real-world applications, though it is incremental as it builds on existing DSST methods.
The paper tackled the problem of real-time visual tracking by proposing a hardware system based on the DSST algorithm, implemented on an FPGA platform, achieving over 153 frames per second with reduced resource usage (33% LUTs and 40% storage blocks).
Visual tracking is one of the most important application areas of computer vision. At present, most algorithms are mainly implemented on PCs, and it is difficult to ensure real-time performance when applied in the real scenario. In order to improve the tracking speed and reduce the overall power consumption of visual tracking, this paper proposes a real-time visual tracking algorithm based on DSST(Discriminative Scale Space Tracking) approach. We implement a hardware system on Xilinx XC7K325T FPGA platform based on our proposed visual tracking algorithm. Our hardware system can run at more than 153 frames per second. In order to reduce the resource occupation, our system adopts the batch processing method in the feature extraction module. In the filter processing module, the FFT IP core is time-division multiplexed. Therefore, our hardware system utilizes LUTs and storage blocks of 33% and 40%, respectively. Test results show that the proposed visual tracking hardware system has excellent performance.