Scalable NoC-based Neuromorphic Hardware Learning and Inference
This work addresses scalability and learning capability issues in neuromorphic hardware for applications requiring brain-like efficiency, but it appears incremental as it builds on existing SNN and NoC concepts.
The authors tackled the problem of limited scale and lack of in-hardware learning in existing spiking neural network (SNN) hardware by proposing a scalable Network-on-Chip (NoC) based architecture with distributed STDP learning, achieving evaluation on MNIST digits.
Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timing-dependent plasticity (STDP) mechanism for learning. Existing hardware implementations of SNN are limited in scale or do not have in-hardware learning capability. In this work, we propose a low-cost scalable Network-on-Chip (NoC) based SNN hardware architecture with fully distributed in-hardware STDP learning capability. All hardware neurons work in parallel and communicate through the NoC. This enables chip-level interconnection, scalability and reconfigurability necessary for deploying different applications. The hardware is applied to learn MNIST digits as an evaluation of its learning capability. We explore the design space to study the trade-offs between speed, area and energy. How to use this procedure to find optimal architecture configuration is also discussed.