Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles
This work addresses the challenge of reducing design iteration time for circuit designers by enabling earlier prediction of violations, though it is incremental as it builds on existing neural network methods.
The paper tackles the problem of predicting design rule violation hotspots in integrated circuit design by proposing a neural network ensemble framework using placement and global routing data, achieving significant performance improvements over a baseline neural network and outperforming random forest in half of test cases.
Design rule check is a critical step in the physical design of integrated circuits to ensure manufacturability. However, it can be done only after a time-consuming detailed routing procedure, which adds drastically to the time of design iterations. With advanced technology nodes, the outcomes of global routing and detailed routing become less correlated, which adds to the difficulty of predicting design rule violations from earlier stages. In this paper, a framework based on neural network ensembles is proposed to predict design rule violation hotspots using information from placement and global routing. A soft voting structure and a PCA-based subset selection scheme are developed on top of a baseline neural network from a recent work. Experimental results show that the proposed architecture achieves significant improvement in model performance compared to the baseline case. For half of test cases, the performance is even better than random forest, a commonly-used ensemble learning model.