Neuromemrisitive Architecture of HTM with On-Device Learning and Neurogenesis
This work addresses the problem of efficient and robust hardware implementation of biomimetic algorithms for researchers and engineers in neuromorphic computing, though it is incremental as it builds on existing HTM methods with specific architectural improvements.
The paper tackled the challenge of implementing Hierarchical Temporal Memory (HTM) efficiently on hardware by proposing a neuromemristive crossbar architecture with on-device learning and neurogenesis, achieving rapid on-chip training within 2 clock cycles and demonstrating suitability for mobile platforms through power analysis.
Hierarchical temporal memory (HTM) is a biomimetic sequence memory algorithm that holds promise for invariant representations of spatial and spatiotemporal inputs. This paper presents a comprehensive neuromemristive crossbar architecture for the spatial pooler (SP) and the sparse distributed representation classifier, which are fundamental to the algorithm. There are several unique features in the proposed architecture that tightly link with the HTM algorithm. A memristor that is suitable for emulating the HTM synapses is identified and a new Z-window function is proposed. The architecture exploits the concept of synthetic synapses to enable potential synapses in the HTM. The crossbar for the SP avoids dark spots caused by unutilized crossbar regions and supports rapid on-chip training within 2 clock cycles. This research also leverages plasticity mechanisms such as neurogenesis and homeostatic intrinsic plasticity to strengthen the robustness and performance of the SP. The proposed design is benchmarked for image recognition tasks using MNIST and Yale faces datasets, and is evaluated using different metrics including entropy, sparseness, and noise robustness. Detailed power analysis at different stages of the SP operations is performed to demonstrate the suitability for mobile platforms.