Low Precision Constant Parameter CNN on FPGA
This work addresses hardware acceleration for deep learning inference, offering incremental improvements in FPGA-based CNN efficiency for specific applications.
The paper tackles efficient FPGA implementation of low-precision CNN convolution layers with sparse and constant parameters, achieving 131 and 23 TOP/chip for corner case blocks and projecting 1.37x higher performance than a V100 GPU for ResNet50.
We report FPGA implementation results of low precision CNN convolution layers optimized for sparse and constant parameters. We describe techniques that amortizes the cost of common factor multiplication and automatically leverage dense hand tuned LUT structures. We apply this method to corner case residual blocks of Resnet on a sparse Resnet50 model to assess achievable utilization and frequency and demonstrate an effective performance of 131 and 23 TOP/chip for the corner case blocks. The projected performance on a multichip persistent implementation of all Resnet50 convolution layers is 10k im/s/chip at batch size 2. This is 1.37x higher than V100 GPU upper bound at the same batch size after normalizing for sparsity.