Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications
This work addresses the problem of hardware design expertise barriers for researchers and developers in mobile deep learning, though it is incremental as it builds on existing FPGA acceleration methods.
The authors tackled the challenge of adapting FPGAs for deep learning in mobile applications by developing a workflow using high-level synthesis tools to ease accelerator design, resulting in an improved SqueezeJet accelerator that speeds up mobile-friendly CNNs like SqueezeNet v1.1 and ZynqNet.
Recently, the field of deep learning has received great attention by the scientific community and it is used to provide improved solutions to many computer vision problems. Convolutional neural networks (CNNs) have been successfully used to attack problems such as object recognition, object detection, semantic segmentation, and scene understanding. The rapid development of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and inference. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low-cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the SqueezeJet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow includes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator. This model can be also used to direct the design process and lead to future design improvements and optimizations.