A Scalable FPGA-based Architecture for Depth Estimation in SLAM
This work addresses the need for efficient, real-time SLAM processing in embedded systems, representing an incremental advance by combining depth estimation with prior tracking work to create a complete accelerator.
The paper tackled the problem of achieving high-performance depth estimation for semi-dense SLAM on low-power embedded systems by developing a scalable FPGA-based accelerator architecture, achieving over 60 frames/sec at 640x480 resolution with an order of magnitude improved power consumption compared to a high-end CPU.
The current state of the art of Simultaneous Localisation and Mapping, or SLAM, on low power embedded systems is about sparse localisation and mapping with low resolution results in the name of efficiency. Meanwhile, research in this field has provided many advances for information rich processing and semantic understanding, combined with high computational requirements for real-time processing. This work provides a solution to bridging this gap, in the form of a scalable SLAM-specific architecture for depth estimation for direct semi-dense SLAM. Targeting an off-the-shelf FPGA-SoC this accelerator architecture achieves a rate of more than 60 mapped frames/sec at a resolution of 640x480 achieving performance on par to a highly-optimised parallel implementation on a high-end desktop CPU with an order of magnitude improved power consumption. Furthermore, the developed architecture is combined with our previous work for the task of tracking, to form the first complete accelerator for semi-dense SLAM on FPGAs, establishing the state of the art in the area of embedded low-power systems.