Protect Your Chip Design Intellectual Property: An Overview
This addresses security risks for fabless semiconductor companies, but it is an incremental overview of existing methods.
The paper reviews techniques for protecting chip design intellectual property against threats like overproduction, piracy, and hardware Trojans in the supply chain, covering logic locking, layout camouflaging, and split manufacturing.
The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.