Neuromorphic In-Memory Computing Framework using Memtransistor Cross-bar based Support Vector Machines
This work addresses the need for low-power, high-density SVM implementations in IoT and edge devices, offering incremental improvements in energy efficiency through novel hardware.
The paper tackles the problem of designing scalable and memory-constrained support vector machines (SVMs) by introducing a framework that removes the positive-definite kernel restriction and allows user-defined memory constraints, achieving classification accuracy comparable to traditional SVMs on benchmark datasets.
This paper presents a novel framework for designing support vector machines (SVMs), which does not impose restriction on the SVM kernel to be positive-definite and allows the user to define memory constraint in terms of fixed template vectors. This makes the framework scalable and enables its implementation for low-power, high-density and memory constrained embedded application. An efficient hardware implementation of the same is also discussed, which utilizes novel low power memtransistor based cross-bar architecture, and is robust to device mismatch and randomness. We used memtransistor measurement data, and showed that the designed SVMs can achieve classification accuracy comparable to traditional SVMs on both synthetic and real-world benchmark datasets. This framework would be beneficial for design of SVM based wake-up systems for internet of things (IoTs) and edge devices where memtransistors can be used to optimize system's energy-efficiency and perform in-memory matrix-vector multiplication (MVM).