Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets
This addresses the critical bottleneck of routing in hardware design, which consumes hours to days for large designs, though it is incremental as it applies an existing GAN method to a specific domain problem.
The paper tackles the problem of predicting routing congestion in physical design by forecasting routing channel densities across the entire floorplan using conditional GANs, achieving results that enable placement exploration and real-time forecasting for eight FPGA designs.
Physical design process commonly consumes hours to days for large designs, and routing is known as the most critical step. Demands for accurate routing quality prediction raise to a new level to accelerate hardware innovation with advanced technology nodes. This work presents an approach that forecasts the density of all routing channels over the entire floorplan, with features collected up to placement, using conditional GANs. Specifically, forecasting the routing congestion is constructed as an image translation (colorization) problem. The proposed approach is applied to a) placement exploration for minimum congestion, b) constrained placement exploration and c) forecasting congestion in real-time during incremental placement, using eight designs targeting a fixed FPGA architecture.