A Low-Power Domino Logic Architecture for Memristor-Based Neuromorphic Computing
This work addresses energy consumption for neuromorphic computing applications, but it appears incremental as it builds on existing memristor and domino logic concepts.
The paper tackled the problem of energy efficiency in memristor-based neuromorphic computing by proposing a domino logic architecture, achieving 0.61 fJ per classification per component and outperforming other designs in energy per accuracy.
We propose a domino logic architecture for memristor-based neuromorphic computing. The design uses the delay of memristor RC circuits to represent synaptic computations and a simple binary neuron activation function. Synchronization schemes are proposed for communicating information between neural network layers, and a simple linear power model is developed to estimate the design's energy efficiency for a particular network size. Results indicate that the proposed architecture can achieve 0.61 fJ per classification per component (neurons and synapses) and outperforms other designs in terms of energy per % accuracy.