Optimized Sharing of Coefficients in Parallel Filter Banks
This work addresses resource efficiency for chip-based signal processing applications, representing an incremental improvement in filter optimization.
The paper tackled the problem of high computational resource usage in parallel filter banks by proposing a novel optimization algorithm that groups filter coefficients in a two-stage process to increase sharing, resulting in up to 50% reduction in registers, look-up tables, and DSP48s without increasing the sampling rate.
Filters are the basic and most important blocks of most signal processing applications. In many applications, a group of parallel filters are used as filter banks. Parallel filter banks naturally require much more computations. Especially on chip applications, the resources are limited and shared among many algorithms. For this purpose, many filter optimization schemes are proposed to reduce the number of resources that filtering operations require. In this work, a novel optimization algorithm is proposed to decrease the number of operations in a group of parallel filters. The filter coefficients are grouped in a two stage process which enables increased coefficient sharing between different filters. The algorithm is capable of decreasing the number of registers, look-up tables and DSP48s by up to 50\% of a regular parallel filter bank, without requiring increased sampling rate.