Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator
This work addresses hardware constraints for efficient DNN accelerators, but it is incremental as it builds on existing FeFET and processing-in-memory concepts.
The paper tackles the problem of device limitations in Ferroelectric FET (FeFET) based in-memory processing architectures for neural networks, exploring design parameters like ADC resolution and bits per cell to quantify their impact on classification accuracy and showing how system architecture and training can mitigate these issues.
In this letter, we quantify the impact of device limitations on the classification accuracy of an artificial neural network, where the synaptic weights are implemented in a Ferroelectric FET (FeFET) based in-memory processing architecture. We explore a design-space consisting of the resolution of the analog-to-digital converter, number of bits per FeFET cell, and the neural network depth. We show how the system architecture, training models and overparametrization can address some of the device limitations.