Hardware Design and Analysis of the ACE and WAGE Ciphers
This work addresses the need for efficient lightweight cryptographic solutions for resource-constrained devices, presenting incremental hardware optimizations for two candidate ciphers.
This paper tackles the hardware design and analysis of ACE and WAGE ciphers for NIST Lightweight Cryptography, reporting area, power, and energy results with ACE achieving up to 4 bits-per-clock cycle and 7260 GE, and WAGE up to 4.57 bits-per-clock cycle and 11080 GE.
This paper presents the hardware design and analysis of ACE and WAGE, two candidate ciphers for the NIST Lightweight Cryptography standardization. Both ciphers use sLiSCP's unified sponge duplex mode. ACE has an internal state of 320 bits, uses three 64 bit Simeck boxes, and implements both authenticated encryption and hashing. WAGE is based on the Welch-Gong stream cipher and provides authenticated encryption. WAGE has 259 bits of state, two 7 bit Welch-Gong permutations, and four lightweight 7 bit S-boxes. ACE and WAGE have the same external interface and follow the same I/O protocol to transition between phases. The paper illustrates how a hardware perspective influenced key aspects of the ACE and WAGE algorithms. The paper reports area, power, and energy results for both serial and parallel (unrolled) implementations using four different ASIC libraries: two 65 nm libraries, a 90 nm library, and a 130 nm library. ACE implementations range from a throughput of 0.5 bits-per-clock cycle (bpc) and an area of 4210 GE (averaged across the four ASIC libraries) up to 4 bpc and 7260 GE. WAGE results range from 0.57 bpc with 2920 GE to 4.57 bpc with 11080 GE.