Hardware/Software Codesign for Training/Testing Multiple Neural Networks on Multiple FPGAs
This work addresses the problem of hardware inflexibility for researchers and engineers deploying neural networks on FPGAs, representing an incremental improvement in hardware/software codesign.
The paper tackles the inflexibility of existing neural network designs for FPGAs by proposing a flexible VHDL structure that enables the implementation, training, and testing of any neural network across multiple FPGAs, using processor groups and a ring buffer for connectivity.
Most neural network designs for FPGAs are inflexible. In this paper, we propose a flexible VHDL structure that would allow any neural network to be implemented on multiple FPGAs. Moreover, the VHDL structure allows for testing as well as training multiple neural networks. The VHDL design consists of multiple processor groups. There are two types of processor groups: Mini Vector Machine Processor Group and Activation Processor Group. Each processor group consists of individual Mini Vector Machines and Activation Processor. The Mini Vector Machines apply vector operations to the data, while the Activation Processors apply activation functions to the data. A ring buffer was implemented to connect the various processor groups.