Machine Learning for high speed channel optimization
This work addresses the need for efficient and accurate optimization in PCB design to lower costs in high-speed electronics, but it appears incremental as it applies an existing method (Bayesian optimization) to a specific domain.
The paper tackles the problem of optimizing printed circuit board (PCB) stack-up parameters for high-speed designs by proposing an efficient global optimization method using parallel and intelligent Bayesian optimization for stripline design, aiming to reduce expensive material choices.
Design of printed circuit board (PCB) stack-up requires the consideration of characteristic impedance, insertion loss and crosstalk. As there are many parameters in a PCB stack-up design, the optimization of these parameters needs to be efficient and accurate. A less optimal stack-up would lead to expensive PCB material choices in high speed designs. In this paper, an efficient global optimization method using parallel and intelligent Bayesian optimization is proposed for the stripline design.