Efficient Hardware Implementation of Incremental Learning and Inference on Chip
This work addresses the need for efficient on-chip incremental learning, which is incremental in nature.
The paper tackles the problem of incrementally learning a classifier directly on chip, achieving state-of-the-art performance through a hardware implementation that accelerates learning and inference compared to a CPU.
In this paper, we tackle the problem of incrementally learning a classifier, one example at a time, directly on chip. To this end, we propose an efficient hardware implementation of a recently introduced incremental learning procedure that achieves state-of-the-art performance by combining transfer learning with majority votes and quantization techniques. The proposed design is able to accommodate for both new examples and new classes directly on the chip. We detail the hardware implementation of the method (implemented on FPGA target) and show it requires limited resources while providing a significant acceleration compared to using a CPU.