Probabilistic spike propagation for FPGA implementation of spiking neural networks
This addresses hardware efficiency for FPGA implementations of spiking neural networks, though it is incremental as it builds on existing methods with specific optimizations.
The paper tackled the bottleneck of fetching synaptic weights in spiking neural networks by introducing a probabilistic spike propagation method, which reduced memory accesses and maintained recognition accuracy with minimal impact on benchmarks like MNIST and CIFAR10.
Evaluation of spiking neural networks requires fetching a large number of synaptic weights to update postsynaptic neurons. This limits parallelism and becomes a bottleneck for hardware. We present an approach for spike propagation based on a probabilistic interpretation of weights, thus reducing memory accesses and updates. We study the effects of introducing randomness into the spike processing, and show on benchmark networks that this can be done with minimal impact on the recognition accuracy. We present an architecture and the trade-offs in accuracy on fully connected and convolutional networks for the MNIST and CIFAR10 datasets on the Xilinx Zynq platform.