Fast inference of Boosted Decision Trees in FPGAs for particle physics
This enables physicists to deploy BDTs in FPGAs for real-time tasks like jet origin identification and muon energy reconstruction in collider experiments, though it is incremental as it builds on existing hls4ml library capabilities.
The paper tackled the problem of high-latency inference for Boosted Decision Trees in particle physics by implementing them in FPGAs using the hls4ml library, achieving a typical latency of less than 100 ns for real-time processing.
We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.