NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework
This addresses the need for faster and more accurate simulation in electronic design automation, enabling better design quality and reduced time-to-market for complex circuits, though it is an incremental improvement by applying neural networks to a known bottleneck.
The paper tackles the problem of slow and inaccurate circuit simulation for large integrated circuits by introducing NN-PARS, a neural network-based parallelized framework that reduces simulation time by over two orders of magnitude compared to a state-of-the-art method while maintaining high accuracy with less than 2% error.
The shrinking of transistor geometries as well as the increasing complexity of integrated circuits, significantly aggravate nonlinear design behavior. This demands accurate and fast circuit simulation to meet the design quality and time-to-market constraints. The existing circuit simulators which utilize lookup tables and/or closed-form expressions are either slow or inaccurate in analyzing the nonlinear behavior of designs with billions of transistors. To address these shortcomings, we present NN-PARS, a neural network (NN) based and parallelized circuit simulation framework with optimized event-driven scheduling of simulation tasks to maximize concurrency, according to the underlying GPU parallel processing capabilities. NN-PARS replaces the required memory queries in traditional techniques with parallelized NN-based computation tasks. Experimental results show that compared to a state-of-the-art current-based simulation method, NN-PARS reduces the simulation time by over two orders of magnitude in large circuits. NN-PARS also provides high accuracy levels in signal waveform calculations, with less than $2\%$ error compared to HSPICE.