A New MRAM-based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision
This addresses the problem of prohibitive training costs for deep neural networks, offering a more efficient hardware solution for AI developers and researchers, though it is incremental as it builds on existing PIM methods.
The paper tackles the high energy and latency costs of DNN training by proposing a new SOT-MRAM-based digital process-in-memory accelerator that supports floating point precision, achieving 3.3x energy, 1.8x latency, and 2.5x area improvements over a state-of-the-art PIM accelerator.
The excellent performance of modern deep neural networks (DNNs) comes at an often prohibitive training cost, limiting the rapid development of DNN innovations and raising various environmental concerns. To reduce the dominant data movement cost of training, process in-memory (PIM) has emerged as a promising solution as it alleviates the need to access DNN weights. However, state-of-the-art PIM DNN training accelerators employ either analog/mixed signal computing which has limited precision or digital computing based on a memory technology that supports limited logic functions and thus requires complicated procedure to realize floating point computation. In this paper, we propose a spin orbit torque magnetic random access memory (SOT-MRAM) based digital PIM accelerator that supports floating point precision. Specifically, this new accelerator features an innovative (1) SOT-MRAM cell, (2) full addition design, and (3) floating point computation. Experiment results show that the proposed SOT-MRAM PIM based DNN training accelerator can achieve 3.3$\times$, 1.8$\times$, and 2.5$\times$ improvement in terms of energy, latency, and area, respectively, compared with a state-of-the-art PIM based DNN training accelerator.