A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification
This work addresses power efficiency for real-time object classification on edge platforms, representing an incremental advance in hardware design.
The authors tackled the problem of high power consumption in neural network hardware for edge devices by proposing a binary-weight spiking neural network architecture, achieving a 7x reduction in area cost and a 23x reduction in energy per classification while improving accuracy on MNIST.
Neural network hardware is considered an essential part of future edge devices. In this paper, we propose a binary-weight spiking neural network (BW-SNN) hardware architecture for low-power real-time object classification on edge platforms. This design stores a full neural network on-chip, and hence requires no off-chip bandwidth. The proposed systolic array maximizes data reuse for a typical convolutional layer. A 5-layer convolutional BW-SNN hardware is implemented in 90nm CMOS. Compared with state-of-the-art designs, the area cost and energy per classification are reduced by 7$\times$ and 23$\times$, respectively, while also achieving a higher accuracy on the MNIST benchmark. This is also a pioneering SNN hardware architecture that supports advanced CNN architectures.