Device-aware inference operations in SONOS nonvolatile memory arrays
This addresses reliability problems in edge AI hardware for applications like IoT, but it is incremental as it builds on existing nonvolatile memory and neural network deployment methods.
The paper tackled device-level noise and retention issues in SONOS nonvolatile memory arrays for edge inference by introducing a mitigation strategy, demonstrating increased resilience to synaptic noise and drift on MNIST, fashion-MNIST, and CIFAR-10 tasks and achieving strong performance with 5-8 bit ADCs.
Non-volatile memory arrays can deploy pre-trained neural network models for edge inference. However, these systems are affected by device-level noise and retention issues. Here, we examine damage caused by these effects, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift. We also show strong performance can be realized with ADCs of 5-8 bits precision.