HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
This work addresses the need for efficient DNN accelerator design tools for both cloud and embedded platforms, though it appears incremental as it builds on existing methods with hybrid techniques.
The authors tackled the problem of accelerating DNN accelerator design by proposing HybridDNN, a framework for building high-performance hybrid DNN accelerators with FPGA implementations, achieving up to 1.8x higher performance compared to state-of-the-art designs, with specific results of 3375.7 GOPS on a high-end FPGA and 83.3 GOPS on an embedded FPGA.
To speedup Deep Neural Networks (DNN) accelerator design and enable effective implementation, we propose HybridDNN, a framework for building high-performance hybrid DNN accelerators and delivering FPGA-based hardware implementations. Novel techniques include a highly flexible and scalable architecture with a hybrid Spatial/Winograd convolution (CONV) Processing Engine (PE), a comprehensive design space exploration tool, and a complete design flow to fully support accelerator design and implementation. Experimental results show that the accelerators generated by HybridDNN can deliver 3375.7 and 83.3 GOPS on a high-end FPGA (VU9P) and an embedded FPGA (PYNQ-Z1), respectively, which achieve a 1.8x higher performance improvement compared to the state-of-art accelerator designs. This demonstrates that HybridDNN is flexible and scalable and can target both cloud and embedded hardware platforms with vastly different resource constraints.