DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks
This work addresses energy efficiency for embedded CNN implementations, but it is incremental as it builds on existing DRAM architectures.
The paper tackled the problem of high DRAM access latency and energy in CNN accelerators by exploring mapping policies on DRAM architectures, resulting in an energy-efficient policy that prioritizes row buffer hits and parallelism.
Many convolutional neural network (CNN) accelerators face performance- and energy-efficiency challenges which are crucial for embedded implementations, due to high DRAM access latency and energy. Recently, some DRAM architectures have been proposed to exploit subarray-level parallelism for decreasing the access latency. Towards this, we present a design space exploration methodology to study the latency and energy of different mapping policies on different DRAM architectures, and identify the pareto-optimal design choices. The results show that the energy-efficient DRAM accesses can be achieved by a mapping policy that orderly prioritizes to maximize the row buffer hits, bank- and subarray-level parallelism.