PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
This addresses the problem of lengthy chip design cycles for VLSI engineers, though it is incremental as it applies existing deep learning methods to a specific domain bottleneck.
The paper tackles the time-consuming iterative process of power grid design in VLSI physical design by introducing a deep learning framework to predict initial power grid designs, reducing prediction error to ~2% and achieving a ~6X speedup in design cycle time.
With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and the training dataset is generated from the floorplans of some of the power grid designs extracted from the IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL-based approach also improves the design cycle time with a speedup of ~6X for standard power grid benchmarks.