Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs
This addresses the challenge of specification errors for SoC designers, but it is incremental as it builds on existing LSTM and mining techniques.
The paper tackles the problem of ambiguous or incomplete specifications in system-on-chip designs by developing a specification mining approach that automatically extracts sequential patterns from transaction-level traces, using LSTM networks and a novel algorithm to characterize system-level specifications, with evaluation on a multi-core SoC prototype showing capability to extract various patterns from highly concurrent traces.
Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However, specifications are often ambiguous, incomplete, or even contain inconsistencies or errors. This paper addresses this problem by developing a specification mining approach that automatically extracts sequential patterns from SoC transaction-level traces such that the mined patterns collectively characterize system-level specifications for SoC designs. This approach exploits long short-term memory (LSTM) networks trained with the collected SoC execution traces to capture sequential dependencies among various communication events. Then, a novel algorithm is developed to efficiently extract sequential patterns on system-level communications from the trained LSTM models. Several trace processing techniques are also proposed to enhance the mining performance. We evaluate the proposed approach on simulation traces of a non-trivial multi-core SoC prototype. Initial results show that the proposed approach is capable of extracting various patterns on system-level specifications from the highly concurrent SoC execution traces.