Securing Digital Systems via Split-Chip Obfuscation
This addresses security issues in IC design for applications relying on untrusted foundries, but it is incremental as it builds on existing split-chip concepts.
The paper tackles the problem of securing integrated circuits against IP privacy and Trojan insertion threats by proposing Split-Chip Obfuscation, which partitions systems between trusted and untrusted fabrication nodes, and develops a design flow with a tool to optimize this partitioning, demonstrated on an example SoC.
Security is an important facet of integrated circuit design for many applications. IP privacy and Trojan insertion are growing threats as circuit fabrication in advanced nodes almost inevitably relies on untrusted foundries. A proposed solution is Split-Chip Obfuscation that uses a combination trusted and untrusted IC fabrication scheme. By utilizing two CMOS processes, a system is endowed with the stronger security guaranties of a trusted legacy node while also leveraging the performance and density of an advanced untrusted node. Critical to the effectiveness of Split-Chip Obfuscation is finding an optimum partitioning of a system between the two ICs. In this paper, we develop a design flow for the Split-Chip Obfuscation scheme, defining the essential system metrics and creating a tool to rapidly assess the large design space. We demonstrate the concept of such a tool and show its application on an example SoC.