Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function
This work addresses security issues in hardware authentication for devices, but appears incremental as it builds on existing attacks and modifications.
The paper tackles the vulnerability of arbiter-based physical unclonable functions (APUFs) to machine learning attacks by proposing a modified design and testing its resistance using logistic regression, with validation on an FPGA board achieving unspecified results.
This paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1).