Logically Synthesized, Hardware-Accelerated, Restricted Boltzmann Machines for Combinatorial Optimization and Integer Factorization
This work addresses the problem of scaling RBMs for practical applications like cryptography and optimization, though it is incremental as it builds on existing RBM methods with hardware-specific enhancements.
The authors tackled the challenge of training Restricted Boltzmann Machines (RBMs) for large-scale NP-hard combinatorial optimization and integer factorization by proposing a method to combine RBMs without full training and optimizing them for hardware acceleration, achieving a 10000x speed improvement and 32x power improvement in factorizing 16-bit numbers on an FPGA.
The Restricted Boltzmann Machine (RBM) is a stochastic neural network capable of solving a variety of difficult tasks such as NP-Hard combinatorial optimization problems and integer factorization. The RBM architecture is also very compact; requiring very few weights and biases. This, along with its simple, parallelizable sampling algorithm for finding the ground state of such problems, makes the RBM amenable to hardware acceleration. However, training of the RBM on these problems can pose a significant challenge, as the training algorithm tends to fail for large problem sizes and efficient mappings can be hard to find. Here, we propose a method of combining RBMs together that avoids the need to train large problems in their full form. We also propose methods for making the RBM more hardware amenable, allowing the algorithm to be efficiently mapped to an FPGA-based accelerator. Using this accelerator, we are able to show hardware accelerated factorization of 16 bit numbers with high accuracy with a speed improvement of 10000x and a power improvement of 32x.