Floating-Point Multiplication Using Neuromorphic Computing
This work addresses the need for floating-point arithmetic in neuromorphic architectures, which is incremental as it adapts existing methods to a new computing paradigm.
The paper tackles the problem of performing IEEE 754-compliant floating-point multiplication in neuromorphic computing systems, achieving results by dividing the process into sub-tasks and optimizing the number of neurons per bit to improve accuracy and reduce bit error rate.
Neuromorphic computing describes the use of VLSI systems to mimic neuro-biological architectures and is also looked at as a promising alternative to the traditional von Neumann architecture. Any new computing architecture would need a system that can perform floating-point arithmetic. In this paper, we describe a neuromorphic system that performs IEEE 754-compliant floating-point multiplication. The complex process of multiplication is divided into smaller sub-tasks performed by components Exponent Adder, Bias Subtractor, Mantissa Multiplier and Sign OF/UF. We study the effect of the number of neurons per bit on accuracy and bit error rate, and estimate the optimal number of neurons needed for each component.