Modeling Techniques for Logic Locking
This addresses the problem of intellectual property piracy in hardware design by exposing and mitigating vulnerabilities in logic locking methods, though it is incremental as it builds on existing attack and defense strategies.
The paper tackles the vulnerability of logic locking to SAT-based attacks by introducing two modeling techniques (relaxed encodings and symmetry breaking) that speed up key discovery by orders of magnitude, reducing attack times from over 15 days to seconds for a state-of-the-art method, and proposes an enhanced locking technique to resist these attacks.
Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.