A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing
This work addresses the need for efficient CNN processing in edge computing, though it is incremental as it builds on existing logarithmic computing methods.
The authors tackled the problem of deploying CNNs on edge devices by proposing a compact processor design using low bit-width logarithmic computing, achieving a processing circuit area of only 0.15 mm² for Yolov2 on TSMC 40 nm technology while maintaining high accuracy.
In this paper, we propose a very compact embedded CNN processor design based on a modified logarithmic computing method using very low bit-width representation. Our high-quality CNN processor can easily fit into edge devices. For Yolov2, our processing circuit takes only 0.15 mm2 using TSMC 40 nm cell library. The key idea is to constrain the activation and weight values of all layers uniformly to be within the range [-1, 1] and produce low bit-width logarithmic representation. With the uniform representations, we devise a unified, reusable CNN computing kernel and significantly reduce computing resources. The proposed approach has been extensively evaluated on many popular image classification CNN models (AlexNet, VGG16, and ResNet-18/34) and object detection models (Yolov2). The hardware-implemented results show that our design consumes only minimal computing and storage resources, yet attains very high accuracy. The design is thoroughly verified on FPGAs, and the SoC integration is underway with promising results. With extremely efficient resource and energy usage, our design is excellent for edge computing purposes.