Placement in Integrated Circuits using Cyclic Reinforcement Learning and Simulated Annealing
This is an incremental improvement for IC physical design, addressing long run times and generalization issues in existing placement tools.
The paper tackles the challenge of placement in integrated circuit design by combining reinforcement learning and simulated annealing to improve initialization and final placement quality, showing that this method leads to better designs compared to other learning-based approaches.
Physical design and production of Integrated Circuits (IC) is becoming increasingly more challenging as the sophistication in IC technology is steadily increasing. Placement has been one of the most critical steps in IC physical design. Through decades of research, partition-based, analytical-based and annealing-based placers have been enriching the placement solution toolbox. However, open challenges including long run time and lack of ability to generalize continue to restrict wider applications of existing placement tools. We devise a learning-based placement tool based on cyclic application of Reinforcement Learning (RL) and Simulated Annealing (SA) by leveraging the advancement of RL. Results show that the RL module is able to provide a better initialization for SA and thus leads to a better final placement design. Compared to other recent learning-based placers, our method is majorly different with its combination of RL and SA. It leverages the RL model's ability to quickly get a good rough solution after training and the heuristic's ability to realize greedy improvements in the solution.