On-Chip Error-triggered Learning of Multi-layer Memristive Spiking Neural Networks
This work addresses the problem of enabling on-chip, in-situ gradient-descent learning for multi-layer SNNs using memristive hardware, which is a significant challenge for neuromorphic computing researchers.
This paper proposes a local, gradient-based, error-triggered learning algorithm with online ternary weight updates for multi-layer Spiking Neural Networks (SNNs). The algorithm enables online training of SNNs with memristive neuromorphic hardware, showing a small loss in performance compared to state-of-the-art methods.
Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradient-descent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multi-layer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared with the state of the art. We also propose a hardware architecture based on memristive crossbar arrays to perform the required vector-matrix multiplications. The necessary peripheral circuitry including pre-synaptic, post-synaptic and write circuits required for online training, have been designed in the sub-threshold regime for power saving with a standard 180 nm CMOS process.