Optimising Design Verification Using Machine Learning: An Open Source Solution
This work aims to reduce the significant time and human expertise required for design verification in the ASIC design flow, which is a critical bottleneck for IC designers.
This paper addresses the challenge of design verification in Integrated Circuits, which consumes nearly 70% of the SoC design cycle. It proposes using Machine Learning to generate input stimulus for verification, aiming for faster and more thorough verification with less human intervention.
With the complexity of Integrated Circuits increasing, design verification has become the most time consuming part of the ASIC design flow. Nearly 70% of the SoC design cycle is consumed by verification. The most commonly used approach to test all corner cases is through the use of Constrained Random Verification. Random stimulus is given in order to hit all possible combinations and test the design thoroughly. However, this approach often requires significant human expertise to reach all corner cases. This paper presents an alternative using Machine Learning to generate the input stimulus. This will allow for faster thorough verification of the design with less human intervention. Furthermore, it is proposed to use the open source verification environment 'Cocotb'. Based on Python, it is simple, intuitive and has a vast library of functions for machine learning applications. This makes it more convenient to use than the bulkier approach using traditional Hardware Verification Languages such as System Verilog or Specman E.