A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses
This work addresses the need for more energy-efficient and faster AI hardware by proposing a novel analog in-memory computing architecture, which could benefit edge AI applications.
This paper proposes an analog in-memory computing (IMC) architecture using spin-orbit torque (SOT) MRAM devices for sigmoidal neurons and binarized synapses. The architecture achieves a 12x reduction in power-area-product for the neuron bitcell and demonstrates 2-4 orders of magnitude performance improvement over mixed-signal IMC and digital GPU implementations for MNIST classification.
In this paper, spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) devices are leveraged to realize sigmoidal neurons and binarized synapses for a single-cycle analog in-memory computing (IMC) architecture. First, an analog SOT-MRAM-based neuron bitcell is proposed which achieves a 12x reduction in power-area-product compared to the previous most power- and area-efficient analog sigmoidal neuron design. Next, proposed neuron and synapse bit cells are used within memory subarrays to form an analog IMC-based multilayer perceptron (MLP) architecture for the MNIST pattern recognition application. The architecture-level results exhibit that our analog IMC architecture achieves at least two and four orders of magnitude performance improvement compared to a mixed-signal analog/digital IMC architecture and a digital GPU implementation, respectively while realizing a comparable classification accuracy.