Overview of FPGA deep learning acceleration based on convolutional neural network
This paper provides a review for researchers and engineers interested in FPGA-based deep learning acceleration, highlighting current trends and limitations.
This review paper surveys the application of FPGAs for accelerating convolutional neural networks, summarizing existing FPGA technologies and their application scenarios. It identifies common issues like under-utilization of logic resources or memory bandwidth that prevent optimal performance.
In recent years, deep learning has become more and more mature, and as a commonly used algorithm in deep learning, convolutional neural networks have been widely used in various visual tasks. In the past, research based on deep learning algorithms mainly relied on hardware such as GPUs and CPUs. However, with the increasing development of FPGAs, both field programmable logic gate arrays, it has become the main implementation hardware platform that combines various neural network deep learning algorithms This article is a review article, which mainly introduces the related theories and algorithms of convolution. It summarizes the application scenarios of several existing FPGA technologies based on convolutional neural networks, and mainly introduces the application of accelerators. At the same time, it summarizes some accelerators' under-utilization of logic resources or under-utilization of memory bandwidth, so that they can't get the best performance.