Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing
This work presents an incremental improvement in energy efficiency and performance for photonic DFRC accelerators, which are relevant for researchers and engineers developing hardware for temporal and sequential machine learning tasks.
This paper proposes a chip-scale delayed feedback reservoir computing (DFRC) accelerator using a silicon photonic microring (MR) based nonlinear neuron and on-chip photonic waveguides. The accelerator achieves significantly lower normalized root mean square error (NRMSE) for time series prediction tasks (35% and 98.7% lower for NARMA10 and Santa Fe respectively) and a 58.8% lower symbol error rate (SER) for Non-Linear Channel Equalization, while also demonstrating 98% and 93% faster training times compared to prior electronic and photonic DFRC accelerators.
To perform temporal and sequential machine learning tasks, the use of conventional Recurrent Neural Networks (RNNs) has been dwindling due to the training complexities of RNNs. To this end, accelerators for delayed feedback reservoir computing (DFRC) have attracted attention in lieu of RNNs, due to their simple hardware implementations. A typical implementation of a DFRC accelerator consists of a delay loop and a single nonlinear neuron, together acting as multiple virtual nodes for computing. In prior work, photonic DFRC accelerators have shown an undisputed advantage of fast computation over their electronic counterparts. In this paper, we propose a more energy-efficient chip-scale DFRC accelerator that employs a silicon photonic microring (MR) based nonlinear neuron along with on-chip photonic waveguides-based delayed feedback loop. Our evaluations show that, compared to a well-known photonic DFRC accelerator from prior work, our proposed MR-based DFRC accelerator achieves 35% and 98.7% lower normalized root mean square error (NRMSE), respectively, for the prediction tasks of NARMA10 and Santa Fe time series. In addition, our MR-based DFRC accelerator achieves 58.8% lower symbol error rate (SER) for the Non-Linear Channel Equalization task. Moreover, our MR-based DFRC accelerator has 98% and 93% faster training time, respectively, compared to an electronic and a photonic DFRC accelerators from prior work.