A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecture
This work aims to reduce latency and power consumption for resource-limited AI end sensing devices by improving processing-in-pixel schemes, which is an incremental improvement.
This paper addresses the high data transfer and power consumption in modern vision systems by proposing a Convolution-in-Pixel CMOS image sensor architecture. The architecture performs convolution before column readout, achieving a computing efficiency of 11.65 TOPS/W (three times higher than conventional schemes) and requiring only 2.5 transistors per pixel.
The separation of the data capture and analysis in modern vision systems has led to a massive amount of data transfer between the end devices and cloud computers, resulting in long latency, slow response, and high power consumption. Efficient hardware architectures are under focused development to enable Artificial Intelligence (AI) at the resource-limited end sensing devices. One of the most promising solutions is to enable Processing-in-Pixel (PIP) scheme. However, the conventional schemes suffer from the low fill-factor issue. This paper proposes a PIP based CMOS sensor architecture, which allows convolution operation before the column readout circuit to significantly improve the image reading speed with much lower power consumption. The simulation results show that the proposed architecture could support the computing efficiency up to 11.65 TOPS/W at the 8-bit weight configuration, which is three times as high as the conventional schemes. The transistors required for each pixel are only 2.5T, significantly improving the fill-factor.