An Efficient Communication Protocol for FPGA IP Protection
This addresses IP protection for FPGA designers and manufacturers, but it is incremental as it builds on existing obfuscation and PUF techniques.
The paper tackles the problem of protecting FPGA intellectual property (IP) cores by proposing a scheme based on FSM obfuscation and PUF for unique device identification, enabling pay-per-device licensing; experimental results on benchmark circuits show it is secure, attack-resilient, and has low overheads in area, power, and delay.
We introduce a protection-based IP security scheme to protect soft and firm IP cores which are used on FPGA devices. The scheme is based on Finite State Machin (FSM) obfuscation and exploits Physical Unclonable Function (PUF) for FPGA unique identification (ID) generation which help pay-per-device licensing. We introduce a communication protocol to protect the rights of parties in this market. On standard benchmark circuits, the experimental results show that our scheme is secure, attack-resilient and can be implemented with low area, power and delay overheads.